EDA Methodology Architect

Responsibilities

• Working directly with core P&R engine developers to define real‐world optimization problems, shape requirements and roadmaps, and provide detailed feedback on engine behavior, QoR, and scalability.
• Defining and rolling out next‐gen flows, including refactoring legacy flows and consolidating ad‐hoc solutions into scalable, maintainable frameworks used across multiple design teams.
• Designing and running rigorous A/B and multi‐variant experiments to compare flows, engines, and tool settings. Developing Python‐based analytics and ML/GenAI techniques to mine large QoR datasets, recommend flow settings, and automate analysis.
• Performing deep root‐cause analysis on QoR issues across engines, tools, and flows, and driving methodologies to resolve the ‘long tail’ of timing closure and performance limiters.
• Partnering with architecture, RTL, DFT, synthesis, physical design, power, signoff, and CAD/methodology teams as a key technical leader and bridge.
• Driving aggressive PPA and schedule targets and the adoption of new tools and flows across the company.
• What we need to see
• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
• 8+ years physical design experience, with deep expertise in industry standard tools like ICC2/Innovus, PrimeTime/Tempus, etc.
• Extensive hands‐on P&R experience taking complex blocks or chips to tape‐out with aggressive PPA targets.

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