Physical Design Engineer, Synthesis and Implementation

Responsibilities

• Own RTL-to-gate synthesis and QoR convergence for complex digital blocks and hierarchical partitions.
• Optimize synthesis strategies, constraints, and flows to meet performance, power, and area targets.
• Analyze design bottlenecks and QoR regressions, collaborating with RTL, timing, architecture, and physical design teams to resolve them.
• Support physical implementation from floorplanning and power planning through routing and timing closure.
• Automate design setup, execution, reporting, and issue triage while improving project-wide methodologies and best known methods.
• What we need to see
• BSEE, MSEE, or equivalent experience.
• 2+ years of experience in synthesis and physical implementation on advanced process nodes.
• Strong proficiency with Synopsys Fusion Compiler, Cadence Genus, or comparable synthesis tools.
• Hands-on experience with synthesis constraints, timing analysis, QoR optimization, and the full place-and-route flow.

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