SoC Verification Lead

Responsibilities

• Own the SoC-level verification plan, schedule, and achievement tracking from the conception of project through tape-out, serving as the primary PIC across all verification workstreams.
• Collaborate with architects, IP owners, emulation team, FPGA team, and infrastructure engineers to align on coverage goals, resolve bottlenecks, and ensure verification requirements are met at every project stage.
• Drive verification status reviews, track open issues across teams, and proactively bring up risks to project leadership with clear mitigation plans.
• Lead risk identification and mitigation planning throughout the verification lifecycle, maintaining clear communication with collaborators.
• Partner with tape-out teams to define and close verification sign-off criteria at each tape-out achievement.
• Define and continuously evolve SoC verification flows and methodologies to meet the demands of next-generation AI-enabled chip complexity.
• What we need to see
• Bachelor’s degree or Master’s degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field.
• 15+ years of hands-on experience in ASIC/SoC functional verification.
• Deep understanding of SoC-level verification challenges and flows — from block integration through full-chip simulation and tape-out sign-off.

Languages