Yerevan · On-siteSalary not disclosedfull-timeVerified recentlySynopsys Careers
You think about synthesis while you write RTL. Timing arcs are not abstract concepts, they are the reason you structured that state machine the way you did.
Responsibilities
Design and implement RTL for digital blocks and subsystems in Verilog/SystemVerilog.
Refine micro-architecture with focus on synthesizability, timing, testability, area, and power tradeoffs.
Drive synthesis and front-end implementation activities.
Support CDC/RDC/Lint signoff readiness and collaborate on design-quality closure.
Work with implementation teams on STA fundamentals, timing constraints, and timing arc understanding.
Collaborate with verification teams on functional debug, test planning, assertions, and coverage.
Support debug and issue resolution using Verdi or similar debug tools.
Participate in design reviews and help resolve integration and interoperability issues across product lines.
Develop automation scripts for design, debug, reporting, and productivity.
