Formal Verification Engineer

Responsibilities

• The specification, implementation, and maintenance of an integrated end-to-end formal verification flow for the formal verification team.
• Developing scripts to automate the verification process.
• Review formal setups and proofs with design and verification teams.
• Maintain and extend assertion libraries, including support for both simulation and FV.
• Identifying key behaviours for verification of DUT and creating a verification plan.
• Developing verification environment including environment assumptions, assertions and cover properties in context of the verification plan.
• Applying various FV techniques to prove correctness of digital designs.
• Debugging RTL to identify causes of failure scenarios.
• What we need to see
• Bachelors/Masters in Electronics & Communications or Computer Science or electrical engineering from a reputed engineering college.

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