Senior Cache Coherency Architect

Responsibilities

• Define consistent interconnect architecture, cache-coherency protocols, and high-performance on-chip interconnect interfaces.
• Contribute to interconnect IP block specifications, build, verification, and integration into the NoC fabric to ensure cache-coherency compliance.
• Collaborate with architects to guarantee the interconnect architecture aligns with project power, performance, and area (PPA) requirements.
• Develop and maintain functional and performance models for the NoC fabric and IP units to assist with analysis and validation.
• Collaborate with cross-functional design and verification teams (simulation, emulation, and formal) to ensure implementations align with architectural specifications.
• Support silicon bring-up and post-silicon debug as needed.
• What we need to see
• Master’s degree in electrical engineering, Computer Engineering, Computer Science, or equivalent experience.
• 5+ years of experience in processor design or other high-performance semiconductor designs.
• Deep understanding of cache coherency, with hands-on experience in industry-standard protocols (e.g., AXI, ACE, CHI).

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