Senior ASIC Timing Engineer, DFT

Responsibilities

• Drive timing analysis and closure for DFT logic on all Nvidia chips (GPUs/CPUs/DPUs/LPUs/SoCs) at all hierarchical levels (block/cluster/full-chip).
• Work with PD, DFX, Clocks and other teams to come up with timing closure strategy, develop timing constraints for custom DFT designs, drive timing and power convergence, and implement ECOs.
• Continuously improve workflows and designs by introducing more automation, resilience, and standardization.
• What we need to see
• BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 2+ years’ experience.
• Hands-on experience in Static Timing Analysis (STA) and driving timing convergence at full-chip/sub-chip level in advanced technology nodes.
• Expertise in analysis and fixing of timing paths through ECOs.
• Expertise in developing timing constraints.
• In-depth knowledge of industry standard timing convergence tools.
• Ways to stand out from the crowd

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