Senior Verification Engineer - HSIO Unit Level

Responsibilities

• You will develop UVM-based verification test benches and methodologies. These will verify complex rapid data transfer IO IPs and sub-systems such as USB, UFS, MPHY, Ethernet, and MACSEC.
• During the course of a project, you will drive the following aspects of verification for your unit
• Architect the testbenches and craft verification environment using SV and UVM methodology
• Define test plans, tests and verification infrastructure for modules, clusters and systems
• Build efficient and reusable bus functional models, monitors, checkers, and scoreboards
• Implement functional coverage and coordinate the verification closure process for the unit
• Work with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust
• What we need to see
• BTech or MTech in ECE, EE, CSE, or an equivalent degree is required. Candidates should have 4+ years of demonstrated ability in verification closure of complex units, sub-systems, or SOC level verification.
• Proven experience in High Speed IO verification (UFS/PCIE/XUSB), knowledge of 10G/1G Ethernet MAC and Switch

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