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ATE Test Engineer

NVIDIA

US, CA, Santa Clara · On-site · relocation$11,000–21,083 gross/mofull-timeNVIDIA Careers (offices abroad)

This is a Test Engineer position supporting the Integrated Circuit Defect Analysis (FA) team. The engineer will enable tailored test equipment and software for the Advantest PS5000 and the Teradyne UltraFLEXPlus (UF+) platforms, while working closely with the product TE team and be embedded in the FA team.

Responsibilities

  • Port and develop test vectors, patterns, and software on the Advantest V93000 system, specifically the PS5000 module, as well as Teradyne UltraFLEXplus platforms.
  • Convert design simulation data (e.g., VCD, EVCD, STIL) into functional, scan, and structural test patterns to recreate IC failures on the tester.
  • Partner with FA engineers, design teams, and test floor technicians to translate physical FA steps like ATE-assisted EMMI or OBIRCH into reproducible, electrical test flows.
  • Improve turnaround time from device failure to root cause by optimizing tester hardware bandwidth, signal integrity, and diagnostic software flows.
  • Design, prototype, and validate custom test hardware (e.g., specialized load boards, probe cards, and device-under-test (DUT) interfaces) for FA setups.
  • What we need to see
  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent experience.
  • 5+ years of hands-on experience with Advantest V93000 (PS5000) (SmarTEST 8 environment) and Teradyne UltraFLEXplus (IG-XL software).
  • Proficiency with script automation (Python, C++, or Perl) and digital vector processing/debug.
  • Familiarity with IC FA flows, failure isolation, electrical fault localization, and yield analysis.

Languages

    Work format
    On-site
    Seniority
    Mid
    Posted
    28 Aug 2026
    Last verified
    In the last 5 days

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