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ASIC Physical Design Engineer

NVIDIA

China, Shanghai · On-site · relocationSalary not disclosedfull-timeNVIDIA Careers (offices abroad)
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ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow. Join us, you will work together with expertise in all these areas; you will not only work for physical application, but also drive physical friendly design with all related teams: ASIC/P&R/DFT/SI/ARCH etc.; you will work for the most advanced process/technology, the biggest chip in the world.

Responsibilities

  • STA for hierarchical design.
  • Constraints creation and validation, timing budget.
  • Timing closure for both partition and full chip level.
  • Special timing closure, such as io, test, clock etc.
  • Synthesis, Netlist quality check, Formal Verification.
  • Implement chip partition and floorplan.
  • Function eco creation.
  • Develop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout).
  • Flow automation development, Methodology in any of above areas.
  • What we need to see

Languages

    Work format
    On-site
    Seniority
    Mid
    Posted
    5 Oct 2026
    Last verified
    In the last 5 days

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