Senior STA Signoff Methodology Engineer

Responsibilities

• Run large-scale SPICE simulations and STA experiments to model the impact of advanced technologies on chip timing.
• Develop STA and PNR flows and recommendations addressing aging, self-heating, thermal effects, IR drop, electro migration, and other advanced-node physical effects.
• Collaborate with technology leads, physical-design engineers, and timing engineers to define and deploy sophisticated timing-signoff strategies for extraordinary silicon performance.
• Develop tools and methodologies that improve design performance, predictability, and silicon reliability beyond the capabilities of standard EDA tools.
• Work across STA, constraints, and timing and power optimization.
• Perform extensive data analysis using Python, JMP, or similar tools to improve STA-to-silicon correlation.
• What we need to see
• MS in Electrical or Computer Engineering, or equivalent experience, with 8 years of experience in ASIC design and timing.
• Solid understanding of RC extraction, device physics, STA methodologies, and EDA-tool limitations.
• Proven foundation in the mathematics and physics underlying electrical design.

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