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Senior Mixed Signal Design Validation Engineer

NVIDIA

US, CA, Santa Clara · On-site · relocation$14,000–25,875 gross/mofull-timeNVIDIA Careers (offices abroad)

NVIDIA's invention of the GPU in 1999 transformed the gaming industry, revolutionized graphics, and sparked the rise of parallel computing. Today, as the driving force behind AI computing, we are leading the charge in creating the technologies that power self-driving cars, robotics, and advanced AI systems.

Responsibilities

  • Lead and drive the creation of validation test plan and test scripts for DDR I/O associated with LPDDR, GDDR, and HBM memory interfaces, ensuring all necessary required analog and digital circuits are covered.
  • Conduct thorough characterization of analog, digital, and mixed-signal circuit blocks under varying conditions (process, voltage, temperature) and correlate results with simulations.
  • Drive system-level validation for memory interfaces, ensuring high-speed performance and quality metrics meet the demanding standards required by our GPU and AI systems.
  • Investigation validating Memory I/O circuit to understand circuit weakness paving ways circuit improvement, architecture enhancement in future products.
  • Lead debugging efforts and design creative solutions to resolve unexpected bugs.
  • Validate silicon performance, quality, and margins for refinement of memory interface designs.
  • Develop and implement test scripts to optimize DDR I/O circuit, sub-circuits and overall system performance
  • Work closely with multi-functional teams, including Mixed signal design, PISI team, hardware, firmware, and Memory qualification engineer, to resolve issues and improve the performance for memory interfaces.
  • Develop and implement tools and scripts to enhance electrical characterization and chip bring-up processes.
  • Mentor and train new engineers on validation practices, encouraging a culture of excellence and continuous improvement.

Languages

    Work format
    On-site
    Seniority
    Senior
    Posted
    27 Feb 2026
    Last verified
    In the last 5 days

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