ASIC Physical Design and Timing Engineer - New College Grad 2026

Responsibilities

• Drive Physical
• Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level.
• Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.
• Play a pivotal role in the success of our innovative projects and advancement of our technology. Work in a cross-functional environment interacting with multiple teams.
• What we need to see
• Master's degree or higher in Electrical or Computer Engineering (or equivalent experience).
• Proficiency in Timing and Static Timing Analysis (STA).
• Hands-on experience in full-chip/sub-chip STA and timing convergence, timing constraints generation and management.
• Expertise with industry standard EDA and timing convergence tools.
• Ways to stand out from the crowd

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