Senior Verification Engineer, PCIE

Responsibilities

• Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.
• Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
• Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.
• You will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.
• What we need to see
• B.Tech./ M.Tech or equivalent experience
• 4+ years of relevant experience
• Experience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog
• Expertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)
• Experience in developing and working in functional coverage based constrained random verification environments

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