Software R&D Engineer, RTL Optimization Tools

Responsibilities

• Invent new methods to enable parallel, graph-based RTL traversal, analysis, and manipulation.
• Devise strategies for rapidly analyzing the impact of RTL changes on data path latency, power, and impact to DFT, clocking, and power delivery.
• Explore use of LLMs (Large Language Models), GNNs (Graph Neural Networks), GANs (Generative Adversarial Networks), and Reinforcement Learning for suggesting or automatically implementing RTL modifications.
• Explore high performance algorithms for clustering, min cost tree covering (technology mapping), datapath implementation and other details of logic synthesis, especially that efficiently incorporate human insight.
• As with any software engineering team, we do write a lot of code, but this is broader than a typical CAD or EDA role. Instead, we as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.…
• What we need to see
• MS or PhD in Electrical Engineering or Computer Science or equivalent experience
• 3+ years of relevant experience in CAD software and VLSI hardware design
• Demonstrated ability in software development with C++, particularly in algorithm development related to graph traversal, pattern matching, and optimization
• Familiarity with RTL design, including Verilog and SystemVerilog code, as well as general hardware design concerns such as scan chain insertion, MBIST, clock and power distribution, and bus architectures

Languages