Senior Power Analysis and Optimization Engineer

Responsibilities

• Analyze full‐chip and unit‐level power using internal and industry‐standard RTL and gate‐level power tools, and translate data into concrete design and architectural improvements.
• Develop and productionize power‐aware models and flows, including ML/RL‐based techniques for anomaly detection, dynamic power management, and design‐space exploration.
• Design and train new LLMs that “learn the art” of power analysis from design data, power reports, bug histories, and best practices—so they can
• Assist engineers in interpreting complex power data
• Propose likely root causes and candidate fixes
• Recommend architectural and micro‐architectural optimizations for power
• Perform comparative power analysis across workloads, products, and design options to identify trends, anomalies, and optimization opportunities that aren’t obvious from first principles alone.
• Partner closely with Architects, Performance, Software, ASIC
• Design, and Physical
• Design teams to interpret power data, root‐cause power bugs, and drive fixes and design changes.

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