Senior Digital Design Verification Engineer - Hardware

Responsibilities

• Verification of the digital design, golden models and micro-architecture of the SerDes IPs using advanced verification methodologies such as UVM.
• Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
• Responsible for understanding the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
• Write and implement test plan and thoroughly verify a design in a product shipment focused / compressed schedule.
• Work with architects, designers, and pre and post silicon verification teams to accomplish your tasks.
• What we need to see
• Bachelors or Masters Degree (or equivalent experience) in Electrical Engineering, Computer Science, or Computer Engineering
• At least 5 years of validated experience.
• Background in verification at Unit/Sub-system/SOC level and expertise in SystemVerilog a must.
• Experience using random stimulus along with functional coverage and assertion-based verification methodologies a must.

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