Physical Verification Engineer

Responsibilities

• Run and analyze physical verification checks such as DRC, LVS, and other tapeout-quality signoff checks.
• Debug physical verification violations and partner with design teams to drive clean closure.
• Review layout, netlist, and runset interactions to identify root causes and recommend fixes.
• Support full-chip and block-level verification readiness across implementation milestones.
• Improve physical verification flow quality, turnaround time, and automation.
• Collaborate with methodology, CAD, and foundry-facing teams on rule interpretation and signoff quality.
• What we need to see
• B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience.
• 2+ years of experience in physical verification, backend implementation, or VLSI signoff.
• Strong understanding of DRC, LVS, antenna, and layout verification concepts.

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