Senior PCIe Design Verification Engineer

Responsibilities

• Verification of the ASIC design, architecture, and micro-architecture of PCIE controllers for multiple product generations for GPUs, SOCs & DPUsat IP/sub-system levels using standard verification methodologies such as UVM and Specman/e.
• Develop UVM or Specman/e based testbench components reusable across verification methodologies and integrate those across verification environments.
• Build or improve reusable testbench components including constraints, stimulus, monitors, checkers and scoreboards following coverage based verification methodology.
• Understand complex testbench and its verification scope with respect to the design specification and implementation, define new verification scope as per design or verification methodology requirements, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.
• Collaborate with multiple verification teams, architects, designers, and pre and post silicon verification teams to accomplish your tasks.
• What we need to see
• Bachelors or Masters degree with 5+ years of experience in Unit/Sub-system/SOC level verification
• Proficiency in SystemVerilog
• Expertise in comprehensive verification of industry standard IP or interconnect protocols (e.g. PCI Express, CXL, UCIe, USB, SATA)
• Experience in developing and working in functional coverage based constrained random verification environments

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