Noise Co-Design Engineer

Responsibilities

• Architect voltage-noise mitigation across the full stack — silicon, package, board, platform, software — and own the co-design trade-offs between them.
• Co-design noise features with Speed, Power, Reliability, Circuit
• Design, Power-Architecture, ASIC, and platform teams. You're the connective tissue across the codesign web.
• Work with other team members to define product-level voltage noise targets, drive them to closure, and sign them off at shipment.
• Build and take ownership of the Sim-to-Si correlation methodology for noise. You know when a model is lying and when silicon is.
• Model and prototype next-gen noise features — transient sense, droop response, mitigation IP, and codify them so every future program inherits them.
• Lead show-stopper noise bugs during bringup. The critical issues stop with you.
• Drive architecture-level codesign tradeoffs across V/F <-> Power <-> Noise <-> Reliability <-> Thermal (Noise-Variation) and (Noise-to-Closure) boundary work, where the highest-leverage innovation lives.
• What we need to see
• BS / MS / PhD in EE, CE, or related (or equivalent experience).

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