Senior Mask Layout Design Engineer

Responsibilities

• Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in groundbreaking sub-micron CMOS technologies using Cadence tools.
• You'll work multi-functional with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
• Take part in floor planning, custom layout and verifying against design rules and schematics.
• What we need to see
• Have a BSEE or equivalent experience. Minimum of 5+ years validated experience in Mask and Layout
• Deep understanding of analog circuit layout concepts in submicron CMOS technologies.
• You are an authority with Cadence custom circuit design tools - particularly virtuoso.
• Experience running and debugging with verification tools such as Dracula, Hercules, Calibre, and Primeyield.
• You are able to work successfully in a team, good interpersonal skills, passion and positive energy.
• Proficient in scripting languages like perl, python, skill etc.

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