Principal System Power Management and Performance Architect

Responsibilities

• The work here is rarely well-defined when it arrives. You will be given problems that appear to be performance gaps or power anomalies and encouraged to build a framework for solving them, not just tackle a single instance.
• Define the multi-generation roadmap for system-level power and performance features, grounded in prototyping, use-case analysis, and cost/benefit trade-offs across segments. You will decide what problems are worth solving and why.
• Own the architecture and integration strategy for HSIO power management, DVFS, P-states, and low-power features. Your decisions improve product performance, power, and reliability across product lines — not just the current program.
• Lead system-level boot and IST architecture defining how power and clock domains initialize, sequence, and recover across complex multi-IP systems where the interaction space is large and the failure modes matter.
• Drive power management strategy at datacenter scale, including rack-level power telemetry and platform state coordination in high-performance environments.
• Identify and redesign system-level processes that break under new product requirements—boot/reset flows, low-power entry/exit sequences, and control-system policies across IPs. When a prior design no longer holds, you diagnose why and architect what comes next.
• Serve as the multi-functional technical authority across architecture, ASIC, board/platform, and firmware teams. You improve the power-performance trade-offs by influencing decisions made by teams you do not control.
• What We Need to See
• We are calibrating for candidates who can carry ambiguous product-level power and performance problems from concept through silicon correlation to release trade-off, and who can show the work!
• BS or MS in EE/CE, or equivalent experience proven through the work itself

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