Chip Power Estimation Engineer

Responsibilities

• Architecture, development and correlation of power estimation models/tools for NVIDIA's chips
• Help architect and develop power models for use-cases, Idle power and IO power.
• Chip in to design the tools based on these models and their testing methodology/infrastructures
• Correlate and Calibrate the power models using measured silicon data
• Analyze and help decide the chip configuration and process technology options to optimize power/performance for NVIDIA's upcoming chips
• Help study and contribute to Performance/Watt improvement ideas for NVIDIA's GPUs and SOCs
• What we need to see
• B.Tech./M.Tech and 2+ years of experience related to Power / Performance estimation and optimization techniques
• Strong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits
• Familiarity with low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS)

Languages