Senior Mixed Signal Design Engineer

Responsibilities

• Mixed-Signal/Analog circuit design for High-Speed Memory I/O Interfaces
• Solve challenges of circuit designs in the latest CMOS FinFET processes
• Take designs through productization and be actively involved in all stages of development
• Work with multi-functional teams to optimize the design
• Contribute to the architecture definition and development of next-generation and future memory systems and interfaces
• What we need to see
• MS/PhD in Electrical Engineering or equivalent experience
• The candidate has 4+ years of well-rounded high-Speed DRAM (LPDDR5/6, DDR4/5, GDDR5/6/7, HBM3/4) or other SerDes interface related design experience.
• In-depth understanding of deep submicron CMOS FinFET process and related circuit design issues
• Familiarity with device reliability, ESD, and Latch-Up requirements

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