Senior Physical Design Engineer

Responsibilities

• Drive physical design and timing from netlist to gds.
• Partner with mixed signal teams to integrate Analog IO’s and macros.
• Work on multi-mode and multi-corner timing closure, RC extraction, Cross talk, IR drop and EM analysis.
• Work with the Front-end teams to create and update timing constraints.
• Perform Physical verification DRC, ERC, LVS, Antenna checks and other checks.
• Debugging timing violations and implementing functional, Timing ECO’s and perform formal verification.
• What we need to see
• BS (or equivalent experience) in Electrical or Computer Engineering with 6+ years' experience or MS (or equivalent experience) with 3+ years' experience in physical design.
• Experienced in Synopsys or Cadence place and route, physical design and timing tools.
• Ability to form methodologies and automate flows.

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