Power Analysis and Optimization Engineer

Responsibilities

• Understand Functionality, Architecture, Feature Algorithm and RTL implementation of IP design.
• Create dedicated IP-level Power model for early power estimation, if any architecture change or new added feature needed.
• Co-work with IP owner to define the power target with different workloads and application scenarios.
• Use internal-developed power flow and analysis tools to look for power saving opportunities; drive IP owner to implement the fixes.
• Explore new methodology to identify more wasted activities in the design and find solutions to save the power.
• Develop automation flow to help improve the efficiency of power analysis.
• What we need to see
• MS with 1~3 years of experience or PhD in related fields.
• Basic understanding of the concept of power and common low power design techniques.
• Familiar with PTPX, PowerArtist and ASIC design flow including RTL coding, synthesis, P&R.

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