SOC Engineering Internship

Responsibilities

• Participate in digital implementation of ASIC designs from RTL to GDSII, covering all major stages
• Conduct gate-level netlist synthesis and logic synthesis, ensuring optimal circuit performance
• Assist in physical implementation, including placement, routing, and optimization of digital circuits
• Support basic static timing analysis to verify timing constraints and design reliability
• Perform basic EMIR (Electromigration and IR drop) checks to ensure robust design
• Carry out physical verifications to guarantee design integrity and manufacturability
• Collaborate with multidisciplinary teams to solve problems and contribute innovative solutions

Languages