Senior Manager, Silicon Speed Productization - Silicon Co-Design Group

Responsibilities

• Close the prediction-to-silicon loop
• Own speed characterization and correlation from pre-silicon planning and first power-on through production sign-off across GPU, CPU, and SoC programs
• Resolve the hardest speed failures
• Drive root-cause closure when a frequency corner does not hold, minimum operating voltage is too high, a critical path escapes timing analysis, or workload behavior diverges from the model
• Define product limits with evidence: Refine methodologies for silicon margining, process-voltage-temperature characterization, guardbanding, aging, and speed binning, and translate the results into product requirements and production decisions
• Left-shift learning: Feed measured-silicon insights back into timing models, critical-path predictions, test content, design practices, and future architectures so that each program begins with a stronger correlation baseline
• Give leadership the clarity to act: Convert characterization data, model deltas, yield trends, and program risks into crisp, decision-ready options for leadership on plan-of-record, qualification, production, and ramp decisions
• Scale analysis and coverage
• Build closed-loop data, automation, and AI-assisted workflows for test orchestration, anomaly detection, triage, and reporting that improve coverage and cycle time
• Build the organization NVIDIA depends on: Hire, develop, and retain a high-performing, globally-distributed team; grow engineers into recognized subsystem experts and develop first-line managers into independent leaders

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