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Senior Reliability Engineer
NVIDIA
US, CA, Santa Clara · On-site · relocation$14,000–22,042 gross/mofull-timeNVIDIA Careers (offices abroad)
For two decades, NVIDIA has pioneered visual computing, the art and science of computer graphics and data centers products. With our invention of the GPU - the engine of innovative visual computing - the field has expanded to encompass personal computer games, movie production, product design, artificial intelligence, medical diagnosis and scientific research.
Responsibilities
- Develop product level reliability qualification plan and implement the qualifications of new NVIDIA products. These include IC chips in AI, Data Center, Mobile, Automotive, Deep Learning, Graphic Processor, and System on Chip sectors. These devices are assembled in either FCBGA, or COWOS, or Multi-Chip Module package.…
- Work closely with design, Customer engineering, product/test engineering and packaging engineering team to develop reliability qualification plan.
- Work closely with DFT team and product engineering team for qualification test program, validation and run data analysis on pre/post reliability stress tests. Work with product engineering team to define device specification and margin study on critical parameters.
- Investigate and analyze data, failures, its failure mechanisms, and develop failure models.
- Drive corrective and preventive actions and project field failures. To effectively handle these tasks, the engineer must have skills in mathematical analysis and reliability modellings to improve product quality and reliability stress-effectiveness.
- Participate in assessment of reliability test requirements for non-conforming materials; and maintain and improve reliability database.
- Have ability to communicate clearly and produce product reliability qualification reports and presentations.
- What we need to see
- Strong technical background in wafer fab with advanced process node, and Flip Chip BGA and COWOS packaging and assembly process technologies.
- You are equipped with knowledge of CMOS/Fin FET devices physics, and familiar with reliability statistics, and models and their failure mechanisms.
Languages
- Work format
- On-site
- Seniority
- Senior
- Posted
- 22 Jul 2026
- Last verified
- In the last 5 days
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