IP Manager, Design and Verification - Networking

Responsibilities

• Lead, mentor, and grow a team of design and verification engineers across a cluster of IP blocks. You will define team structure, hiring plans, and career development paths to build a strong, scalable organization.
• Own the end-to-end execution of IP delivery — micro-architecture, RTL design, functional verification, coverage closure, assertions, formal verification, and synthesis handoff. You will set quality bars, review schedules, and drive milestone adherence across your IP cluster.
• Define and drive verification strategies, test plans, coverage goals, and sign-off criteria for your IPs. Your team will develop UVM-based constrained-random and directed test environments, achieve functional and code coverage targets, and ensure robust regression infrastructure.
• Partner with architecture, SoC integration, physical design, DFT, firmware, and software teams to resolve cross-functional dependencies, close interface specifications, and ensure seamless IP integration. We will look to you to identify risks early, drive trade-off decisions, and align technical priorities across…
• Establish and improve design and verification methodologies, best practices, reuse strategies, and automation flows to increase team productivity and IP quality across tape-outs.
• What We Need To See
• B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience.
• 10+ years of experience in ASIC/SoC design or verification, including 2+ years in a people management or technical leadership role managing multi-engineer teams.
• Strong understanding of digital design fundamentals — RTL coding (Verilog/SystemVerilog), micro-architecture, timing, clocking, reset, power management, and synthesis constraints.
• Strong understanding of verification methodologies — e-specman/UVM, constrained-random verification, coverage-driven verification, assertions (SVA), and formal verification techniques.

Languages