Memory Mask Design Engineer

Responsibilities

• Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm,5nm, 7nm and lower nodes following industry standard methodologies.
• Deliver layouts for Full Custom Memory group specializing in digital Memory circuits.
• IP layout will comprise of significant digital components.
• Adopting and putting in place the best layout practices/methodology for composing digital Memory layouts
• Follow company procedures and practices for IC layout activities.
• What we need to see
• B.E/B Tech. / M Tech in Electronics or equivalent experience with 2+ Years of proven experience in Memory layout in advanced CMOS process.
• Detailed knowledge of industry standard EDA tools for Cadence.
• Experience with layout of high-performance memories of various types.
• Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding)

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