Senior DFT Methodology Engineer

Responsibilities

• As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, I1149.1, I1500, I1687, 1838, memory BIST, memory dump and DFX security methodology.
• You will partner closely with timing, physical design, software, bring-up, and production teams to make the right trade-offs between cost and quality.
• In addition, you will help architect, develop and deploy DFT methodologies for our next generation products including RTL design, Verification, pattern generation, partnering with teams like timing, physical design, software, bringup, production
• You will also help mentor junior engineers on test designs and trade-offs including cost and quality.
• What we need to see
• BS/MS Electrical or Computer Engineering (or equivalent experience) in related domain with proven DFT experience
• 10+ years of hands-on experience in SoC architecture, RTL design, and verification.
• Strong analytical skills, with experience using vendor tools to verify and validate test patterns and logic on highly complex, multi-million-gate designs.
• Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power, to ensure we are making the right trade-offs
• Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development

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