SOC Clock Distribution Engineer

Responsibilities

• Designing and implementing SOC level clock requirements
• Daily work involves aspects of chip level design, including partitioning, CDC, trial synthesis, design quality checks
• Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, resolve design quality issues
• What we need to see
• B.SC. in Electrical Engineering/Computer Engineering.
• 3+ years of confirmed experience in chip design
• Shown hands on physical design skills in clock distribution in tight multi power and timing/layout constrained products.
• Proficiency in at least one common scripting languages like perl, python, bash, Tcl.
• Phenomenal teammate.
• Ways to stand out from the crowd

Languages