Mixed-Signal Design Engineer - RTL and Co-Simulation

Responsibilities

• Build and run co-simulations that connect digital RTL with analog circuits or SPICE and Verilog-A models.
• Enhance and maintain the RTL for the power controller’s full digital control loop.
• Verify startup, steady-state, transient, calibration, and fault behavior at the system level in either a purely digital or a co-simulation environment.
• Debug issues across the analog–digital boundary with analog and digital designers.
• Develop RTL behavioral models for mixed-signal blocks.
• Design and implement control, protection, fault-handling, and calibration features.
• What we need to see
• B.S. or MS degree in Electrical Engineering (or equivalent experience)
• 1-3 years of work on analog–digital co-simulation and digital RTL design for a power controller.
• Experience designing and debugging synthesizable Verilog or SystemVerilog RTL.

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