Low-Power Feature Validation & Bring-Up Engineer

Responsibilities

• Define the Power & Performance validation strategy across product lines, including power targets, rail budgets, and low-power feature validation methodologies.
• Build intelligent workload characterization frameworks that use telemetry, behavioral clustering, and AI-assisted analytics to improve validation coverage and expose power-state and data-path issues earlier in the development cycle.
• Define the instrumentation, counters, telemetry frameworks, and firmware hooks needed to support scalable silicon observability, automated validation, and AI-powered debug workflows prior to tapeout.
• Bring up and validate system-level low-power features across pre-silicon and post-silicon environments using sophisticated automation, data-driven validation methodologies, and generative AI-assisted debug techniques.
• Develop AI/ML-assisted infrastructure for telemetry analysis, anomaly detection, predictive validation analytics, workload optimization, automated triage, and cross-generation debug correlation.
• Partner closely with architecture, firmware, DV, HSIO, system integration, and data infrastructure teams to build scalable validation pipelines, intelligent dashboards, and modern engineering workflows for next-generation silicon platforms.
• Support manufacturing and customer-facing teams in resolving production and feature issues using telemetry-powered insights, automated analytics, and scalable debug methodologies.
• Work across hardware, software, firmware, and platform teams to drive low-power feature readiness from early architecture definition through silicon bring-up, validation, and product release.
• What We Need to See
• BS/MS in EE, CE, CS, Systems Engineering, or equivalent experience.

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