Senior SOC Clocks RTL Design Engineer

Responsibilities

• Acting as the technical lead for SOC clocks development — leading the implementation of the clocking logic from specification through tape-out and bring-up
• Working with the architecture and micro-architecture teams on the SOC clock and reset scheme: collecting clocking requirements from units across the chip, feeding back implementation and timing considerations, and translating the agreed scheme into a verifiable design
• Writing and reviewing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization
• Leading and mentoring other RTL engineers working on clocking: reviewing designs, setting coding and quality standards, and distributing work across the team
• Working hand-in-hand with the Physical
• Design (backend) team on clock tree implementation, SDC/timing constraints, partitioning, floorplan feedback, trial synthesis, and timing convergence
• Partnering with
• Design Verification on clocking testplans, functional and gate-level debug, and coverage closure
• Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows
• Representing clocking implementation in cross-functional design reviews with architecture, PD, DV, DFT, and CAD stakeholders

Languages