System Verification Co-Design Engineer - Speed and Rel

Responsibilities

• Collaborate cross-functionally with system architects, hardware, firmware/software, process/reliability, and operations teams to co-design system-level speed features and deliver industry-defining products.
• Understand system level behavior and speed reliability margins, bounding box constraints and identify solutions that optimize margins.
• Translate hardware features and architectural requirements into verification techniques that achieve full coverage across testing flows.
• Perform closed loop validation by correlating silicon behavior against timing simulation and design expectations; provide actionable feedback to improve future designs.
• Define, prototype, and refine pre- and post-silicon bring-up flows to ensure product quality, performance, and schedule efficiency.
• Design and implement automation tools for system speed modeling; apply AI and LLM-assisted workflows (e.g., automated log analysis, pattern detection, scripting acceleration) to compress characterization and debug cycles.
• Architect and influence testability features critical to performance, power, and reliability in partnership with design, DFx, and ATE teams.
• Lead debug of complex silicon and system-level issues, including show-stopper defects, to enable on-time product shipment.
• What We Need to See
• MS in EE, CE, Systems Engineering, or equivalent experience.

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