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Silicon Validation Engineer
NVIDIA
US, CA, Santa Clara · On-site · relocation$11,333–18,208 gross/mofull-timeNVIDIA Careers (offices abroad)
NVIDIA Silicon Co-design Group is seeking a versatile engineer to join the HW ArchDev Methodology team. SCG operates across the full product lifecycle—from early architecture definition through silicon bring-up to production—providing a unique end-to-end perspective on next-generation systems You define how validation is done.
Responsibilities
- Design system-level validation strategies for complex architectures, corner cases, PVT, large-scale behavior, feature interactions
- Build AI-assisted and data-driven validation workflows that improve coverage, debug turnaround, and efficiency
- Profile real workloads: training, inference, HPC, video, and emerging applications
- Deploy automation and telemetry pipelines that scale across products and teams
- Drive silicon bring-up and root-cause debug with reusable, high-leverage methods
- What we need to see
- BS/MS in EE/CE (or equivalent experience)
- 4+ years in silicon bring-up, ASIC validation, or system-level debug
- Grounding in PVT, timing (STA), signal integrity, power, and high-speed IO (PCIe, chip-to-chip)
- Understanding of firmware/driver-hardware interaction
Languages
- Work format
- On-site
- Seniority
- Mid
- Posted
- 13 Oct 2026
- Last verified
- In the last 5 days
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