Senior ASIC Verification Engineer

Responsibilities

• Design and maintain the unit level/sub-system Verification environment.
• Understand the architecture specifications, develop and carry out the test plan to verify the design.
• Create UVM components, sequences, tests and scoreboards.
• Sign off on the verification efforts with very high-quality code and functional coverage.
• Launch regressions, resolve the issues, and make forward progress towards achieving the DV milestone targets
• Automate the manual steps involved in launching build, regression, and triage.
• Collaborate with architects, designers, and software engineers to achieve project goals.
• Proactively contributes to improving the efficiency of the testbenches by embracing the latest techniques.
• Responsible for end-to-end verification of IPs, ensuring the highest quality delivery.
• What we need to see

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