Senior Mask Design Engineer - Hardware

Responsibilities

• You'll collaborate cross functionally with package technical lead (PTL) and I/O signal integrity and technology engineers to deliver solution for product packages in tight schedule.
• Performing physical layout for silicon interposer using Cadence tools.
• Conduct design feasibility studies to evaluate the package design goals for size, cost, and system performance.
• Take part in studying layout floorplan and perform custom layout and verification against design rules and netlists.
• Propose layout design trade-offs to the PTL for resolution and implementation.
• ​What we need to see
• Hold a B.S. Electrical Engineering or equivalent experience
• Minimum of 5+ years proven experience in Mask and Layout
• Deep understanding of layout concepts in submicron CMOS technologies.
• You are an authority with Cadence layout tools - particularly Virtuoso.

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