Senior ASIC Design Engineer - Memory Subsystem

Responsibilities

• As a member of our Memory Subsystem
• Design team, you will collaborate with architects/design verification/formal verification/physical design team to deliver a world-class solution. NVIDIA SOC Interconnects, ordering controllers and memory accelerators are among the industry's most sophisticated because of the complex area, latency, power, bandwidth and…
• In this position, you will have the opportunity to be responsible for the micro-architecture and design including RTL design, synthesis and timing analysis using innovative CAD tools and using the latest process technologies.
• What we need to see
• BS or MS in Electrical Engineering or Computer Engineer or related degree (or equivalent experience)
• 5+ years of experience
• Experience with high-speed coherent interconnects, protocol bridges, hardware-managed coherency and system level caches is a plus
• Experience with multiple clock domains and asynchronous interfaces is a plus
• Knowledge of industry specifications like CHI/CXL/PCI-E is a plus.
• Strong proficiency of Verilog or VHDL.

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