ASIC Design and Verification Intern, SOC - 2027

Responsibilities

• Participate in RTL design and verification of SysASIC and clock-related IPs
• Develop and debug Verilog/SystemVerilog RTL, testbenches, assertions, and simulation regressions.
• Analyze and resolve issues from simulation, formal verification, lint, CDC/RDC, synthesis, STA, and gate-level verification.
• Collaborate with cross-functional teams to improve design quality, verification coverage, and development efficiency.
• Develop scripts, automation tools and AI agent to improve design and verification flows.
• What We Need to See
• Pursuing a BS/MS degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Understanding of digital logic design and front-end ASIC development flow, including RTL design, simulation, synthesis, STA, lint, and CDC/RDC.
• Familiarity with clocking concepts, such as clock gating, clock-domain crossing, reset synchronization, PLLs, and timing fundamentals.
• Proficiency in Verilog and/or SystemVerilog; knowledge of UVM, SVA, or functional coverage is a plus.

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