Senior Memory Post Silicon Qualification Engineer

Responsibilities

• Build memory qualification as a repeatable, AI-accelerated capability. Every program generates large datasets of shmoo, margin, and characterization data. Turn that data into decision-ready insight faster than any single engineer can, and shift memory-issue detection left so we catch problems before they hit ramp!
• Own functional validation, IO tuning, timing margin analysis, and multi-vendor DRAM qualification across the memory controller, PHY, and DRAM device — for the full matrix of capacities, speeds, and configurations we ship.
• Lead root-cause closure on the hardest multi-team memory failures — spanning silicon, controller, PHY, package, board SI/PI, firmware, and workload — with reusable workarounds and productized fixes.
• Design and deploy AI-enabled workflows for margin data analysis, shmoo bucketing, failure signature detection, and workload-vs-margin correlation — with the guardrails to make the outputs trustworthy enough to gate qualification decisions.
• Partner with pre-Si architecture, design, and DV teams to translate new memory features into targeted post-Si validation plans, and feed post-Si learnings back into pre-Si methodology.

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