Senior Physical Design and Timing Engineer

Responsibilities

• Drive physical design and timing of high-frequency and low-power NVIDIA CPUs, GPUs, LPUs and SoCs at block level, cluster level, and/or full chip level.
• Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.
• Work in a cross-functional environment interacting with multiple teams.
• What we need to see
• BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years of experience, or MS (or equivalent experience) with 3+ years of experience in physical design, synthesis, and timing.
• Strong hands-on experience taking complex blocks, IPs, or chips from RTL/netlist to tapeout through logic synthesis, floorplanning, placement, clock-tree synthesis, routing, physical optimization, signoff, and ECOs.
• Demonstrated success improving power, performance, and area through design improvements, critical-path planning and crafting, or methodology/workflow improvements.
• Hands-on experience in block, sub-chip, and full-chip level Static Timing Analysis, timing-constraint development, and multi-mode, multi-corner timing closure factoring in process variations, IR drop, and Xtalk.
• Expertise and in-depth knowledge of industry-standard EDA tools.
• Proficiency in Python, Tcl, Perl, Make, or similar scripting languages as well as AI/ML/DL/LLMs.

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