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PMU ASIC Engineer - New College Graduate 2027

NVIDIA

China, Shanghai · On-site · relocationSalary not disclosedfull-timeNVIDIA Careers (offices abroad)

As chip sizes continue to grow, power efficiency(token per watt/dollar) has become critical across all NVIDIA products - from data centers to automotive and personal computing. Our PMU IP, developed over the past 17 years, is essential in optimizing chip performance and efficiency in both idle and active scenarios.

Responsibilities

  • Implement the micro-architecture to RTL design.
  • Handling the general chip sign off checklist for every milestone
  • Involve into the discussion with the architecture member or even the SW member for the motivation
  • What we need to see
  • BS / MS in electrical / Microelectronics/ Integrated Circuits engineering.
  • Strong communication skills and proficient oral English since this role require frequent communication with external teams mainly in USA and India.
  • Familiar with frontend ASIC design.
  • Ways to stand out from the crowd
  • Experience on thermal management/active power/low power design. For example, NAFLL ADC, AVFS, DVFS, PG/RG/CG, etc.
  • Play similar role in other system-level control features if not power related.

Languages

    Work format
    On-site
    Seniority
    Junior
    Posted
    12 Oct 2026
    Last verified
    In the last 5 days

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