Senior DFT Engineer - Hardware

Responsibilities

• POR to Post Silicon Testing of DFX features for high speed IOs. This includes crafting of test features crucial for manufacturing testability of HighSpeed IOs. Architect
• Design & Validate these test features with a robust & scalable testplan development at unit-level and SOC/Full Chip level using verification methodologies like UVM and NVIDIA Internal tools. Pre-Silicon Simulation and Debug of Test functionality using standard Industry tools and sign off on Test coverage for various…
• Ability to work on automation, flow development & improvement, coverage metrics, test execution, bug identification/fix and IO-test productization.
• Solve complex Test problems in the mixed-signal world and develop a scalable test solution that works across platforms.
• Work with powerful Industry-standard tools for
• Design and verification methodologies along with SV, UVM, Perl, Python and adapt to NVIDIA custom tools/flows.
• Partnering closely with our IP teams for design/verification of IOBIST test-logic, Collaborating with Mixed Signal Circuit design teams to understand the analog design components in an IO cell.
• Collaborate with other DFX teams, coordinate with Post Silicon Test Engineering and Production Engineering teams for productizing quality test at efficient test cost.
• What we need to see
• Btech/BE/BS or Mtech/ME/MS in EE/ECE or equivalent experience

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