Senior DFT Power Methodology Engineer

Responsibilities

• As a senior member in our team, you will work on innovating in the DFT Power, Thermal & Voltage Noise Methodology areas.
• This will include working on groundbreaking low power & thermal solutions for our manufacturing tests to be enabled at conditions that push the boundaries for our datacenter GPUs.
• Partner with multi-functional teams including Product Development & Power Architecture, implementing brand-new methodologies on hard-to-solve problems for improving our outgoing quality of chips.
• You will work on post-silicon data analysis for power to architect the next-gen solutions.
• In addition, you will help develop and deploy DFT methodologies for our next generation products using Applied ML & Gen AI solutions.
• Help mentor junior engineers on test designs and trade-offs including cost and quality.
• What we need to see
• BSEE (or equivalent experience) with 12+, MSEE with 10+, or PhD with 6+ years of experience in DFT design & power
• Understanding of fundamental DFT topics and VLSI areas of power, timing & voltage noise
• Experience in Power Analysis, Thermal Analysis & IR Drop tools is a plus.

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