VLSI CAD Timing Intern, Applied AI - Summer 2027

Responsibilities

• Learn and support static timing analysis (STA) flows using industry tools like PrimeTime and Tempus for advanced ASIC designs.
• Help develop and automate timing, constraints, and QoR validation flows using scripting and data-driven methods.
• Assist with analyzing timing reports, constraints, and design data across corners and modes to improve closure predictability.
• Collaborate with CAD, physical design, and methodology engineers on timing sign-off strategies and best practices.
• Contribute to early AI- or analytics-assisted approaches for timing analysis, constraint checking, or flow optimization.
• Explore how physical effects (e.g., IR drop, crosstalk, aging, thermal impact) influence timing and design decisions.
• What we need to see
• Currently pursuing a Master’s or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Coursework or academic knowledge in VLSI/ASIC design, digital circuits, or computer architecture.
• Exposure to applying agentic AI to back-end VLSI tasks (e.g., floorplanning, timing closure, or physical verification).

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