Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Responsibilities

• As a member of our CPU team, you'll be responsible for synthesis and achieving timing, area, performance and power goals of the on-chip interconnect network and last-level caches.
• Help evaluate the physical design for next-generation Nvidia coherent interconnects and system-level caches.
• What we need to see
• Master’s Degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience.
• 5+ years of experience in processor or other related high-performance semiconductor designs.
• Physical design expertise in high-frequency design, including hands-on synthesis experience, timing analysis, floor-planning and in-depth knowledge of industry standard physical design tools is required.
• Experience in interconnect/cache/core design is desirable.
• Verilog expertise is preferred as is a deep understanding of ASIC design flow including RTL design and verification, DFT, and ECO.
• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.
• NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power-efficient chips in their class? If so, we…

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