Senior Digital Design Engineer

Responsibilities

• As a key member of the NVLink Fusion design team, you will analyze the architectural requirements, perform the trade-off analysis for implementation, and deliver high performance, area and power efficient RTL Blocks.
• Craft micro-architecture specification, implement in high-quality RTL, and deliver a fully verified, synthesis and timing clean block.
• Collaborate with chip architects, verification engineers, formal verification engineers, and SoC integration engineers in order to meet the goals of the block in a timely manner
• Identify potential IP solutions for specific use cases and assist in selecting, customizing and integrating the right IP solutions.
• What we need to see
• Bachelors or Master's Degree, or equivalent experience in Electrical Engineering or Computer Engineering
• 5+ years of relevant work experience.
• Experience working with high-speed connectivity protocols such as NVLink, PCI-Express, Ethernet, UCIE etc.
• Proven track record of delivering high bandwidth datapath blocks such as data movers, protocol adaptors, network-on-chip, arbiters and schedulers etc.
• Deep understanding of ASIC design flows and methodology

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